1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor device that has a field effect transistor having a high dielectric constant gate insulating film, and a manufacturing method of such a semiconductor device.
2. Background Art
In order to realize higher integration, higher performance, and a higher operation speed of semiconductor integrated circuit devices, various technologies for improving transistor driving capability have been proposed. One of the technologies is a technology of increasing inversion-layer capacitance by reducing the thickness of a SiO2 film and a SiON film (silicon oxynitride film) as a gate insulating film.
However, a thinner gate insulating film causes an increased tunneling current between a substrate and a gate electrode, resulting in increased power consumption.
In view of this problem, a technology has been proposed in which, instead of a SiO2 film and a SiON film, a high dielectric constant film that is mainly made from an oxide of a high dielectric constant material such as hafnium (Hf), zirconium (Zr), and aluminum (Al) is used as a gate insulating film.
Hereinafter, a technology disclosed in Japanese Laid-Open Patent Publication No. 2003-69011 will be described with reference to the figures. More specifically, a semiconductor device that has a field effect transistor (FET) using a high dielectric constant film as a gate insulating film and a manufacturing method of such a semiconductor device will be described.
FIG. 12 schematically shows a semiconductor device 10 disclosed in Japanese Laid-Open Patent Publication No. 2003-69011. The semiconductor device 10 includes a FET having a high dielectric constant gate insulating film.
A P-conductivity type monocrystalline silicon (Si) substrate 11 of (100) orientation is used in the semiconductor device 10. First, an element isolation insulating region 12 is formed to define an active region in the substrate 11. Implantation of P-conductivity type ions for adjusting the substrate concentration, ion implantation for adjusting the threshold voltage, and heat treatment for activation are then conducted according to known technologies.
Thereafter, a high dielectric constant gate insulating film is formed. First, an Al2O3 film is formed by an ALCVD (Atomic Layer Chemical Vapor Deposition) method using trimethylaluminum (Al(CH3)3) and H2O as a row material gas and an oxidizing gas, respectively. A SiO2 film of 0.5 nm thick is then formed by an ALCVD method using Si2H6 and H2O. A composite film 13 of the Al2O3 film and the SiO2 film is thus formed.
A SiO2 film 14 of 0.6 nm thick is then formed between the Al2O3 film of the composite film 13 and the substrate 11 by an RTO (Rapid Thermal Oxidation) process in O2.
An in-situ phosphorus-doped polycrystalline Si film of 100 nm thick is then formed on the substrate 11. The phosphorus-doped polycrystalline Si film is heat treated at 750° C. for five minutes in a nitrogen atmosphere, and then, patterned into a gate electrode 15 by a known technology such as etching.
By using the gate electrode 15 as a mask, arsenic (As) ions are perpendicularly implanted into the substrate 11 on both sides of the gate electrode 15. As a result, an extension region 16, a shallow diffusion layer, is formed. For example, the acceleration energy is 3 keV and the dose is 1×1015/cm2 in this ion implantation.
The extension region 16 has a lower As ion concentration than that of source and drain regions that are to be formed later. The extension region 16 is formed to reduce the electric field in the channel direction in the transistor.
By using the gate electrode 15 as a mask, boron (B) ions are perpendicularly implanted into a region under the extension region 16 in order to form a pocket region 17. The pocket region 17 is a P-conductivity type diffusion layer for preventing punch-through. For example, the acceleration energy is 10 keV and the dose is 4×1015/cm2 in this ion implantation.
A silicon oxide film of 50 nm thick is then deposited at a low temperature (400° C.) so as to cover the substrate 11 and the gate electrode 15. The silicon oxide film is then selectively etched by anisotropic dry etching so that the silicon oxide film is left only on the sidewall of the gate electrode 15. A sidewall 18 is thus formed.
By using the gate electrode 15 and the sidewall 18 as a mask, As ions are implanted into the substrate 11 on both sides of the sidewall 18 in order to form a source region and a drain region (hereinafter, referred to as source/drain regions 19). The source/drain regions 19 are N-type high concentration diffusion layers. In this ion implantation, the acceleration energy is 30 keV and the dose is 2×1015/cm2.
Nitrogen annealing is then conducted at 1,000° C. for five seconds in order to activate the implanted ions.
A thin cobalt (Co) film is then deposited by a sputtering method so as to cover the substrate 11, the gate electrode 15, and the like. Thereafter, annealing is conducted at 500° C. for a short period of time in order to silicide the Co film on the portions where silicon is exposed, that is, on the gate electrode 15 and the source/drain regions 19. The unreacted Co film on the element isolation insulating region 12, the sidewall 18 and the like is removed with a mixture of hydrochloric acid and a hydrogen peroxide solution. A Co silicide film 20 is thus formed. Heat treatment is then conducted for a short period of time in order to reduce the resistance of the Co silicide film 20.
A thick silicon oxide film is then deposited, and the surface of the silicon oxide film is planarized by chemical mechanical polishing. A surface protection insulating film 21 is thus formed. An opening is formed in a prescribed region of the surface protection insulating film 21. A titanium nitride (TiN) film and a tungsten (W) film are then deposited as a wiring barrier material and a wiring metal, respectively. Planarization is then conducted so that the W film remains only in the opening region. Thereafter, according to a required circuit structure, a metal film that is mainly made from aluminum is deposited and patterned to form wirings 22 for the gate, source, and drain.
In this way, an N-channel FET using a high dielectric constant film as a gate insulating film is formed.